-- Copyright James McGill, 2010
-- Author: James McGill (jmcgill@plexer.net)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY mock_ram_test IS
END mock_ram_test;
 
architecture behavior OF mock_ram_test IS 
    -- UUT
    COMPONENT mock_ram
    PORT(
         address : IN  std_logic_vector(15 downto 0);
         data : OUT  std_logic_vector(7 downto 0);
         clock_1mhz : IN  std_logic;
         clock_8mhz : IN  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal address : std_logic_vector(15 downto 0) := (others => '0');
   signal clock_1mhz : std_logic := '0';
   signal clock_8mhz : std_logic := '0';

 	--Outputs
   signal data : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clock_1mhz_period : time := 1000 ns;
   constant clock_8mhz_period : time := 125 ns;
 
begin
   uut: mock_ram PORT MAP (
          address => address,
          data => data,
          clock_1mhz => clock_1mhz,
          clock_8mhz => clock_8mhz
        );

   -- Clock process definitions
   clock_1mhz_process :process
   begin
		clock_1mhz <= '0';
		wait for clock_1mhz_period/2;
		clock_1mhz <= '1';
		wait for clock_1mhz_period/2;
   end process;
 
   clock_8mhz_process :process
   begin
		clock_8mhz <= '0';
		wait for clock_8mhz_period/2;
		clock_8mhz <= '1';
		wait for clock_8mhz_period/2;
   end process;
end;
